The present invention relates generally to non-volatile memory devices and, more particularly, to a method and system for providing dual protection for a one-time programmable (xe2x80x9cOTPxe2x80x9d) sector in a simultaneous flash electrically erasable programmable memory (xe2x80x9cEEPROMxe2x80x9d).
Computers, personal digital assistants, cellular telephones and other electronic systems and devices typically include processors and memory. The memory is used to store instructions (typically in the form of computer programs) to be executed and/or data to be operated on by the processors to achieve the functionality of the device. In some applications, the systems and devices may require that the instructions and/or data be retained in some form of a permanent/non-volatile storage medium so that the information is not lost when the device is turned off or power is removed. Exemplary applications include computer BIOS storage and diskless handheld computing devices such as personal digital assistants.
Flash memories are popular memory storage devices because they store information in the absence of continuous power and are capable of being constructed in a very compact form. Flash memory is typically constructed by fabricating a plurality of floating gate transistors in a silicon substrate. A floating gate transistor is capable of storing electrical charge either on a separate gate electrode, known as a floating gate, or in a dielectric layer underlying a control gate electrode. Generally speaking, data is stored in a non-volatile memory device by the storage of an electrical charge in the floating gate.
In order to program and/or erase a flash memory, typically a complex process must be followed. For example, before erasing a particular sector, that sector must be programmed (known as xe2x80x9cpre-programmingxe2x80x9d). Erasing and programming sectors and cells involves complex application of high voltages to the memory cells for specified periods of time and in particular sequences. Many flash memories provide embedded state machines that perform the complex programming and erasing operations automatically. These processes of programming and erasing a flash memory may take a long time to complete. A typical erase sequence can take anywhere from 0.7 seconds up to 15 seconds. To erase an entire chip can take up to 49 seconds. While programming is much faster, on the order of seven to 300 microseconds, it is still slow compared to other memory devices. Programming an entire chip can take up to seven seconds (including the time to verify the data). Typically, standard Dynamic Random Access Memory (xe2x80x9cDRAMxe2x80x9d) offers access times on the order of nano-seconds, a difference between microseconds of many orders of magnitude.
This complex nature of programming and erasing flash memory devices leads to a major problem in that they do not provide sufficiently fast random access. For example, conventional flash memory devices typically do not allow a processor to perform a read operation while a program or erase operation is underway in the flash memory device. In most implementations, the processor is required to periodically poll a status register of the flash memory device to detect the end of the program or erase operation before initiating a read operation to the flash memory device.
Unfortunately, as noted above, the programming and erase cycle times for typical flash memory are orders of magnitude greater than acceptable write access times of a conventional random access main memory using DRAM. Such long latencies associated with programming or erase operations can lock up the operating system and prevent the system from functioning for unacceptably long time intervals if the flash memory is the only memory in the electronic system. Some prior flash memories allow erase-suspend operations in order to address this problem. Erase suspend allows the processor to pause an erase operation so another sector can be read. However, such memories typically still impose a suspend latency interval of several microseconds before a read operation can be initiated. A typical suspend latency interval is from 0.1 to 20 microseconds.
Prior systems may employ multiple flash memory devices in an attempt to prevent such operating system lock-up. In such systems, the processor usually has read access to one of the flash memory devices while other flash memory devices are undergoing a program or erase operation. However, such systems typically suffer from high costs because multiple flash memory devices are implemented even though the capacity of a single flash memory device may accommodate the needs of the particular electronic device.
Another prior art system uses a flash memory in combination with an EEPROM memory. This system allows a read operation of one of the memories while writing to the other. However, the size of an EEPROM memory cell is significantly larger than that of a flash memory cell that reduces the amount of storage that can be placed on the memory chip. Further, there are significant design and manufacturing complexities involved with integrating two different memory technologies on the same chip. Therefore, a device that uses an EEPROM in combination with a flash memory will typically be more expensive both to design and manufacture.
In addition, programming and erasing a flash memory involves higher than normal voltages as compared to performing read operations. The use of these higher-than-normal voltages can cause problems when trying to implement the capability to simultaneously read while programming/erasing. Such problems include difficulties in distributing the high voltages required for the program and erase operations along with normal voltage for read operations and handling increased noise induced on the read sense outputs by the use of high voltages elsewhere within the device. Further, depending on the implementation, redundant logic may also be employed which introduces further complexities.
A new type of flash memory has recently been developed that is capable of providing simultaneous read and write operations. In this type of flash memory, the memory device is divided into two or more banks. Each bank includes a number of sectors and each sector includes a set of memory cells. Each bank has a respective decoder circuit that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read-sense amplifier or a verify-sense amplifier. The read-sense amplifier connects to the output buffer while the verify-sense amplifier connects to the state machine. When one bank receives a write command (program or erase), the internal state machine takes control and starts the program or erase operation. While one bank is busy with the program or erase operation, the other bank can be accessed for reading data.
For a detailed discussion of sliding bank architecture, see U.S. Pat. No. 5,867,430 entitled xe2x80x9cBANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITINGxe2x80x9d and U.S. Pat. No. 5,847,998 entitled xe2x80x9cNON-VOLATILE MEMORY ARRAY THAT ENABLES SIMULTANEOUS READ AND WRITE OPERATIONS,xe2x80x9d which are herein incorporated by reference.
As known to those skilled in the art, flash memory may be used to store various types of information. In general, the information can be divided into two categories, code and data. Code corresponds to program code that is used to execute various operations that the flash memory is capable of performing. Data generally corresponds to fields of data that changes more frequently than code. Because code rarely, if ever, changes in lifetime of some devices, it is desirable to have the ability to write-protect sectors that store code, while leaving some sectors unprotected. Providing a write-protect function allows manufacturers to ensure that data does not mistakenly get written into a sector that is designated for code.
In some peripheral devices that use flash memory, it is necessary to ensure that a predetermined sector absolutely cannot be erased or re-programmed. As such, a one-time programmable (xe2x80x9cOTPxe2x80x9d) sector may be incorporated into a memory device. Due to the importance of the content stored in the OTP sector, a method and system is needed to ensure the security of the data that is stored in the OTP sector. A common example of a peripheral device that uses OTP sectors is mobile communication devices, such as cellular or digital mobile telephones.
To that end, a need exists for a simultaneous operation flash memory that is capable of providing dual write protection for an OTP sector.
The present invention discloses a simultaneous operation flash memory with dual write protection for an OTP sector. The preferred simultaneous operation flash memory includes a plurality of sectors that are divided into an upper bank and a sliding lower bank. Each bank contains at least one sector and the size of each bank may be adjusted during fabrication depending on the particular requirements set forth. The simultaneous operation flash memory is capable of write-protecting respective sectors in either the upper or sliding lower bank. Thus, irrespective of which bank a particular sector is fabricated in, the simultaneous operation flash memory is capable of write-protecting predetermined sectors, or groups of sectors, depending on the way the sectors are decoded.
In the preferred embodiment of the present invention, the simultaneous operation flash memory also locks out a predetermined sector, so that the sector cannot be erased or re-programmed by the user after being fabricated and programmed to include code data. As set forth above, some peripheral devices that use flash memory have generated a need for memory manufacturers to include at least one sector that is designated as an OTP sector. The flash memory cells in the OTP sector are programmed during fabrication and then locked out after testing so that the user cannot change the data content of the OTP sector.
The simultaneous operation flash memory includes at least one OTP sector write-protect CAM that is electrically connected with a respective lower sector select line that is used to decode the OTP sector. As known in the art, a CAM is a content addressable memory that can be used to store data. The OTP sector write-protect CAM is associated with a predetermined sector by way of its association with a respective decoder circuit. In the preferred embodiment of the present invention, if the OTP sector write-protect CAM is programmed, the OTP sector is read only. If the OTP sector write-protect CAM is in an erased state, the OTP sector is not write protected and may be erased and re-programmed.
The preferred simultaneous operation flash memory further includes at least one OTP sector lock CAM that is electrically connected with the OTP sector write-protect CAM. As previously set forth, if the simultaneous operation flash memory is manufactured with an OTP sector, there is a strong desire to be able to ensure write protection of the data stored in the OTP sector. The OTP sector lock CAM is used to ensure that the OTP sector operates as read only, by locking out the ability to erase the OTP sector write-protect CAM. To that end, the OTP sector lock CAM assures that the OTP sector write-protect CAM cannot be erased once programmed, which would indicate that the OTP sector is not write-protected. Therefore, the present invention discloses a simultaneous operation flash memory that is capable of providing dual write protection to the OTP sector.
In the preferred embodiment of the present invention, if the OTP sector write-protect CAM is in an erased state, the user can change the data stored in the OTP sector. When the simultaneous operation flash memory is being fabricated, the OTP sector is programmed and then tested to ensure that the data has been programmed into the OTP sector properly. As such, while the OTP sector is being programmed during fabrication, the OTP sector write-protect CAM is in an erased state; and, while the OTP sector is being tested, the OTP sector write-protect CAM is in a programmed state to ensure that the data programmed into the OTP sector cannot be changed during testing. After the simultaneous operation flash memory has completed in-house testing, the OTP sector lock CAM is programmed, which does not allow the OTP sector to be written to again by forcing the OTP sector write-protect CAM to remain in the programmed state at all times.
In the preferred embodiment, the status of the OTP sector write-protect CAM is dependent on the status of the OTP sector lock CAM. If the OTP sector lock CAM is programmed, the OTP sector write-protect CAM cannot be erased. As such, the user cannot change the data in the OTP sector. Thus, the present invention provides double security to the OTP sector because the OTP sector lock CAM prevents the OTP sector write-protect CAM from being erased, which in turn, prevents the OTP sector 26 being erased and re-programmed. As previously set forth, if the OTP sector write-protect CAM is in a programmed state, the OTP sector is designated to operate in a read-only state and will not be erased or programmed.